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| SS12 thru SS115 Schottky Barrier Rectifiers PRODUCT SUMMARY 1.0AMP Surface Mount SMA/DO-214AC FEATURES For surface mounted application Easy pick and place Metal to silicon rectifier, majority carrier conduction Low power loss, high efficiency High current capability, low VF High surge current capability Plastic material used carriers Underwriters Laboratory Classification 94V-0 Epitaxial construction High temperature soldering: 260 oC / 10 seconds at terminals Dimensions in inches and (millimeters) MECANICAL DATA Case: JEDEC SMA/DO-214AC Molded plastic Terminals: Pure tin plated, lead free Polarity: Indicated by cathode band Packaging: 12mm tape per EIA STD RS-481 Weight: 0.066 gram Pb-free; RoHS-compliant 12/12/2007 Rev.1.00 www.SiliconStandard.com 1 SS12 thru SS115 MAXIMUM RATINGS AND ELECTRICAL CHARACTERISTICS o Ratings at 25 C ambient temperature unless otherwise specified. Single phase, half wave, 60 Hz, resistive or inductive load. For capacitive load, derate current by 20% Type Number Maximum Recurrent Peak Reverse Voltage Maximum RMS Voltage Maximum DC Blocking Voltage Maximum Average Forward Rectified Current at TL(See Fig. 1) Peak Forward Surge Current, 8.3 ms Single Half Sine-wave Superimposed on Rated Load (JEDEC method ) Maximum Instantaneous Forward Voltage o (Note 1) IF= 1.0A @ 25 C o @ 100 C o Maximum DC Reverse Current @ TA =25 C at o Rated DC Blocking Voltage @ TA=125 C Maximum DC Reverse Current at VR=33V o & TA=50 C Typical Junction Capacitance (Note 3) Typical Thermal Resistance ( Note 2 ) Symbol SS 12 20 VRRM 14 VRMS 20 VDC I(AV) IFSM VF IR HTIR Cj SS 13 30 21 30 SS 14 40 28 40 SS 15 50 35 50 SS 16 60 42 60 SS 19 90 63 90 SS 110 100 70 100 SS Units 115 150 V 105 V 150 V A A 1.0 30 0.5 0.4 0.4 10 50 o 0.75 0.65 5.0 0.80 0.95 0.70 0.85 0.1 2.0 5.0 V mA mA uA pF C/W o o R JL 28 88 R JA Operating Temperature Range TJ -65 to +125 -65 to +150 Storage Temperature Range TSTG -65 to +150 Notes: 1. Pulse Test with PW=300 usec, 1% Duty Cycle 2. Measured on P.C.Board with 0.2" x 0.2" (5.0mm x 5.0mm) Copper Pad Areas. 3. Measured at 1 MHz and Applied Reverse Voltage of 4.0V D.C. C C 12/12/2007 Rev.1.00 www.SiliconStandard.com 2 SS12 thru SS115 RATINGS AND CHARACTERISTIC CURVES FIG.1- MAXIMUM FORWARD CURRENT DERATING CURVE 1.0 50 RESISTIVE OR INDUCTIVE LOAD SS12- SS14 SS15-SS115 0.5 FIG.2- MAXIMUM NON-REPETITIVE FORWARD SURGE CURRENT PEAK FORWARD SURGE CURRENT. (A) AVERAGE FORWARD CURRENT. (A) 40 AT RATED TL 8.3ms Single Half Sine Wave JEDEC Method 30 20 10 PCB MOUNTED ON 0.2X0.2" (5.0X5.0mm) COPPER PAD AREAS 0 50 60 70 80 90 100 110 120 130 o 0 140 150 160 170 1 LEAD TEMPERATURE. ( C) 10 NUMBER OF CYCLES AT 60Hz 100 FIG.3- TYPICAL FORWARD CHARACTERISTICS 100 50 FIG.4- TYPICAL REVERSE CHARACTERISTICS SS12-SS14 SS15-SS115 INSTANTANEOUS REVERSE CURRENT. (mA) SS19-SS110 10 SS15-SS16 INSTANTANEOUS FORWARD CURRENT. (A) 10 SS12-SS14 Tj=125 0C 1 1 SS115 0.1 Tj=75 0C 0.1 0.01 Tj=25 C O PULSE WIDTH=300 S 1% DUTY CYCLE 0.01 0 .2 .4 .6 .8 1.0 1.2 1.4 1.6 FORWARD VOLTAGE. (V) 0.001 0 20 40 60 80 100 120 140 PERCENT OF RATED PEAK REVERSE VOLTAGE. (%) FIG.5- TYPICAL JUNCTION CAPACITANCE TRANSIENT THERMAL IMPEDANCE. (OC/W) 400 Tj=25 0C f=1.0MHz Vsig=50mVp-p FIG.6- TYPICAL TRANSIENT THERMAL CHARACTERISTICS 100 JUNCTION CAPACITANCE.(pF) 100 SS12-SS14 SS15-SS16 SS19-SS115 10 1 10 0.1 1.0 10 100 0.1 0.01 0.1 1 10 T, PULSE DURATION. (sec) 100 REVERSE VOLTAGE. (V) Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 12/12/2007 Rev.1.00 www.SiliconStandard.com 3 |
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